// ******************************************************************************
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_pciedma_ns_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2
// History       :  xxx 2021/10/23 09:27:29 Create file
// ******************************************************************************

#ifndef __STARS_PCIEDMA_NS_REG_REG_OFFSET_H__
#define __STARS_PCIEDMA_NS_REG_REG_OFFSET_H__

/* STARS_PCIEDMA_NS_REG Base address of Module's Register */
#define SOC_STARS_PCIEDMA_NS_REG_BASE                       (0x2c18000)

/******************************************************************************/
/*                      SOC STARS_PCIEDMA_NS_REG Registers' Definitions                            */
/******************************************************************************/

#define SOC_STARS_PCIEDMA_NS_REG_STARS_PRIORITY_CTRL0_REG               (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x0)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PRIORITY_CTRL1_REG               (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x4)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PRIORITY_CTRL2_REG               (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x8)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PRIORITY_CTRL3_REG               (SOC_STARS_PCIEDMA_NS_REG_BASE + 0xC)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_FRIENDLY_CTRL_REG                (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x20)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_FSM_SEL_REG              (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x810)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_FSM_STATE_REG            (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x814)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_REDUNDANT_RSP_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x820)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_FREE_PCIEDMA_CORE_BITMAP_REG     (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x824)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CFG_FSM_STATE_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x828)  /* PCIEDMA配置加速器状态机状态寄存器 */
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_DFX_CNT_ENABLE_REG       (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x830)  /* PCIEDMA调度器任务总数统计使能寄存器 */
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_DFX_TASK_VLD_CNT_REG     (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x834)  /* PCIEDMA调度器下发任务总数 */
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_DFX_TASK_RSP_CNT_REG     (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x838)  /* PCIEDMA调度器收到加速器完成响应总数 */
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_POOL_ENABLE_CTRL_NS_REG  (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x840)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_POOL_DISABLE_CTRL_NS_REG (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x880)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_POOL_STATUS0_NS_REG      (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x8C0)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_0_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1000)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_1_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1040)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_2_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1080)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_3_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x10C0)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_4_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1100)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_5_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1140)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_6_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1180)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS0_7_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x11C0)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_0_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1004)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_1_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1044)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_2_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1084)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_3_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x10C4)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_4_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1104)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_5_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1144)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_6_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1184)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS1_7_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x11C4)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_0_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1008)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_1_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1048)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_2_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1088)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_3_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x10C8)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_4_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1108)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_5_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1148)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_6_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1188)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS2_7_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x11C8)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_0_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x100C)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_1_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x104C)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_2_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x108C)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_3_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x10CC)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_4_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x110C)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_5_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x114C)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_6_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x118C)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CQE_STATUS3_7_REG        (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x11CC)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CTRL0_REG                (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1800)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CTRL1_REG                (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1804)
#define SOC_STARS_PCIEDMA_NS_REG_STARS_PCIEDMA_CTRL2_REG                (SOC_STARS_PCIEDMA_NS_REG_BASE + 0x1808)

#endif // __STARS_PCIEDMA_NS_REG_REG_OFFSET_H__
